pci-dual channel ultra160 scsi controller overview the symbios SYM53C1010 is a highly integrated pci-dual channel ultra160 scsi controller. the SYM53C1010 is 100 percent compatible with the ultra160 scsi initiative and provides additional features that ensure robust ultra160 system operation. the SYM53C1010 provides a seamless migration path from the sym53c896 pci-dual channel ultra2 scsi controller with pin compatibility. figure 1. scsi on the motherboard applications servers internet/intranet network, video, e-mail, printing, database management, and financial applications workstations cad/cam, industrial simulation, etc. host attach for raid and jbod mass storage subsystems anywhere data access is the bottleneck symbios SYM53C1010 controller benefits provides complete end-to-end protection of the scsi i/o with cyclic redundancy check (crc) and asynchronous information protection (aip) provides robust performance with surelink domain validation migrates easily from ultra2 scsi supports all major operating systems protects scsi investments paves the way to ultra320 scsi host pci bridge 64-bit, 33/66 mhz primary pci bus flash (up to 1 mb) nvram (2) SYM53C1010 pci-ultra160 scsi scsi scsi ultra160 scsi bus
new ultra160 scsi features double transition clocking enables throughput of up to 160 mbps on each channel for a total of 320 mbps, without increasing the interface clock rate. cyclic redundancy check (crc) improves the reliability of scsi data trans- mission through enhanced detection of communication errors. crc provides extra data protection for marginal cable plants and external devices. crc is the best way to ensure data protection during hot plugging. it uses the same proven crc algorithm used by fddi, ethernet, and fibre channel, and detects all single bit errors, all double bit errors, all odd number of errors, and all burst errors up to 32 bits long. to provide complete end-to-end protection of the scsi i/o, aip protects all non-data phases, augmenting the crc feature of ultra160. surelink domain validation technology detects the configuration of the scsi bus and automatically tests and adjusts the scsi transfer rate to optimize inter- operability. the SYM53C1010 exceeds ultra160 by providing not only basic (level 1) and enhanced (level 2) domain validation, but adds margined (level 3) domain validation. this enhancement margins lvd drive strength and clock signal timing characteristics to identify marginal ultra160 systems. hardware/software overview pci interface the host pci interface complies with pci local bus specification revision 2.2, and implements a 64-bit/66 mhz pci bus. it is backward compatible with 32-bit/33 mhz buses. additionally, support for dac is provided. the SYM53C1010 is a true pci multifunction device in that it presents one electrical load to the pci bus. it uses one req/-gnt/pair to arbitrate for pci bus mastership, and separate interrupt signals are generated for scsi function a and scsi function b for maximum performance. the SYM53C1010 complies with pci power management interface specification revision 1.1 and pc 99, supporting power states d0, d1, d2, d3hot and d3cold, power management capabilities registers, and programmable values for pci subsystem vendor id and subsystem id. extended access cycles (memory read line, memory read multiple, and memory write and invalidate) are also supported. scsi processors the SYM53C1010 provides two independent ultra160 scsi controllers on a single chip. each controller supports wide ultra160 scsi synchronous transfer rates up to 160 mbps on a lvd scsi bus. integrated lvdlink transceivers support both lvd and single-ended signals with no external transceivers symbios SYM53C1010 controller features pin compatible with sym53c896 controller design board to accommodate either device in the same socket op code (software) compatible no external memory required 64-bit, 33/66 mhz pci interface theoretical 528 mbps (on 66 mhz part) zero wait state transfer rate 64-bit addressing supported through dual address cycle (dac) compliant with pci 2.2, pci power management 1.1 and pc99 supports ultra160 scsi double transition clocking for 160 mbps throughput on each channel cyclic redundancy check domain validation asynchronous information protection covers all non-data, including command, status and messages high-performance pci multifunction device presents one electrical load to pci bus two independent wide ultra160 scsi channels scsi interrupt steering logic (sisl) alternate interrupt routing for raid applications supports nextreme raid
required. fast scsi, ultra scsi, ultra2 scsi, and ultra160 scsi are all supported by the SYM53C1010. an on-chip scsi clock quadrupler allows the chip to achieve ultra160 scsi transfer rates with an input frequency of 40 mhz. the 8 kb of internal ram per channel for scripts instruction storage allow all accesses to remain internal, reducing the time spent on the pci bus. a 944-byte dma fifo on each channel allows the device to efficiently burst up to 512 bytes across the pci bus. scsi bus phase mismatches are handled in scripts, reducing cpu utilization. figure 2. SYM53C1010 functional signal grouping features (continued) proven integrated lvdlink transceivers for direct attach to either low voltage differential (lvd) or single-ended (se) scsi buses comprehensive surelink domain validation basic (level 1) with inquiry command enhanced (level 2) with read/ write buffer margined (level 3) with margining of lvd drive strength and programmable skew test ieee 1149.1 jtag boundary scan flash and local memory interface packaged in a 329 pbga supported in symbios storage device management system (sdms ) software release 4.6 full operating system support: - windows?nt?2000 and 95/98 - linux - solaris - unixware - novell?netware - os/2 server management cl (component instrumentation) clk rst/ req/ gnt/ req64/ ack64/ ad[63:0] c_be[7:0]/ idsel frame/ irdy/ trdy/ devsel/ stop/ perr/ serr/ par par64 inta/ intb/ alt_inta/ alt_intb/ int_dir m66en enable66 sclk rbias a_sd[15:0]/ a_sdp[1:0]/ a_diffsens a_gpio0_fetch/ a_gpio1_master/ a_gpio2 a_gpio3 a_gpio4 b_gpio0_fetch/ b_gpio1_master/ b_gpio2 b_gpio3 b_gpio4 mwe/ mce/ moe/_testout mas0/ mas1/ mad7-0 329 pbga SYM53C1010 64-bit, 66 mhz pci scsi function a a_sc_d/ a_si_o/ a_smsg/ a_sreq/ a_sreq2/ a_sack/ a_sack2/ a_sbsy/ a_satn/ a_srst/ a_ssel/ b_sd[15:0]/ b_sdp[1:0]/ b_diffsens b_sc_d/ b_si_o/ b_smsg/ b_sreq/ b_sreq2/ b_sack/ b_sack2/ b_sbsy/ b_satn/ b_srst/ b_ssel/ test_rstn test_hsc moe/_testout tck tms tdi tdo test_pd scan_mode scsi function b test interface scsi function a gpio scsi function b gpio memory interface symbios SYM53C1010 controller
visit our web site at http://symbios.lsilogic.com lsi logic corporation north american headquarters milpitas, ca tel: 408.433.8000 fax: 408.433.8989 lsi logic europe ltd european headquarters united kingdom tel: 44.1344.426544 fax: 44.1344.481039 lsi logic kk headquarters tokyo, japan tel: 81.3.5463.7821 fax: 81.3.5463.7820 symbios SYM53C1010 controller lsi logic logo design, symbios, and tolerant are registered trademarks, and lvdlink, nextreme, scripts, sdms, and surelink are trademarks of lsi logic corporation. all other brand and pro duct names may be trademarks of their respective companies. lsi logic corporation reserves the right to make changes to any products and services herein at any time without notice. lsi logic does not assume any responsibility or liability aris- ing out of the application or use of any product or service described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase, lease, or use of a product or service from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intel- lectual property rights of lsi logic or of third parties. copyright ?2000 by lsi logic corporation. all rights reserved. order no. s20010 6/00-500 printed in usa iso 9000 certified memory lnterfaces the SYM53C1010 supports up to 1 mb of external expansion rom through a parallel interface, for add-in card designs. for ease of software development and field upgrades of the rom, the interface supports local programming of flash memory. a serial 2-wire interface on each scsi channel provides a connection to an external serial eeprom for storing subsystem vendor id and subsystem id. software the SYM53C1010 is supported with the proven sdms software. sdms software enables the performance enhancements of ultra160 data transfer speed increases and improved pci bus utilization capabilities included in the SYM53C1010. the SYM53C1010 reliability capabilities of aip and crc are enabled and managed by the sdms software. sdms software implements the manageability improve- ments of the lsi logic surelink domain validation technology. surelink technology extends standard domain validation with the addition of full cable plant margining. the cable plant margining capability, exclusive to lsi logic s ultra160 solution, includes end-to-end margining from the SYM53C1010 through lsi logic s sym53c180 scsi bus expander to the target device. the domain validation capability of sdms software is available as an independent application as well as integrated in the dmi 2.0 based system management solution for enterprise class implementations. sdms software includes bios and osv certified drivers for all major operating systems including dos with aspi support, windows 95/98, windows nt/2000, unixware, os/2, netware, solaris and linux. a complete set of scsi utilities rounds out the software solution, which includes a dmi 2.0 based system management software for windows nt, netware, unixware, solaris and linux, and a stand-alone or snap-in dmi browser applet and surelink applet. figure 3. SYM53C1010 functional block diagram ultra160 scsi controller block host pci bus (64-bit, 33/66 mhz) pci master and slave control block, pci configuration registers (2 sets), and scsi arbitration 8 dword scripts prefetch buffer 8 kb scripts ram 944-byte dma fifo scsi scripts processor opening registers scsi fifo and scsi control block tolerant and lvdlink ultra160 scsi controller block 8 dword scripts prefetch buffer 8 kb scripts ram 944-byte dma fifo scsi scripts processor opening registers scsi fifo and scsi control block tolerant and lvdlink jtag serial eeprom controller and auto-configuration rom/flash memory control local memory bus jtag wide ultra160 scsi bus (a channel) 2-wire serial eeprom bus (one per channel) rom/flash memory bus wide ultra160 scsi bus (b channel)
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